1. Field of the Invention
The present invention relates to a method of manufacturing a metal interconnection of a semiconductor device. More particularly, the present invention relates to a damascene process used to form metal interconnections of a semiconductor device.
2. Description of the Related Art
Copper (Cu) is widely used for forming metal interconnections of highly integrated semiconductor devices. Although the resistivity of aluminum (Al) is about 2.67 μΩ·cm, the resistivity of copper is 1.69 μΩ·cm. Therefore, the lower resistivity of Cu allows Cu patterns to transmit signals at higher rates than similar Al patterns. In addition, Cu patterns have a great resistance to electromigration (EM), which enhances the reliability of semiconductor devices. Furthermore, Cu is a useful material for forming interconnections because the power consumption of Cu is relatively small and Cu is less expensive as a raw material than Al.
However, it is not easy to etch copper, making it very difficult to pattern a copper layer into a desired shape. Therefore, Cu interconnections are made by forming openings of a desired shape in an interlayer dielectric layer, subsequently forming a layer of Cu over the interlayer dielectric layer to fill the opening with Cu, and removing the unnecessary portion of the copper layer by chemical mechanical polishing (CMP) or the like. This entire process is referred to as a damascene process. In particular, a double damascene process is widely used to form Cu interconnections. This involves forming a via and a trench over the via in an interlayer insulating layer, then forming a Cu layer over the interlayer insulating layer to fill the via and the trench simultaneously, and then planarizing the copper layer.
FIGS. 1A through 1G illustrate a conventional method of forming a copper interconnection by a dual damascene process.
Referring to FIG. 1A, a semiconductor substrate 10 has a conductive layer 20 formed thereon. An interlayer dielectric layer 24 is formed over the semiconductor substrate 10. The interlayer dielectric layer 24 is etched to form an opening 26 that exposes a conductive element of the conductive layer 20. In this respect, an etch stop layer 22 may be used to prevent the conductive element 20 from being etched when the opening 26 is formed in the interlayer dielectric layer 24.
Referring to FIG. 1B, a conductive barrier layer 30 is formed on the inner walls of the interlayer dielectric layer 24 that define the opening 26, and on the upper surface of the interlayer dielectric layer 24.
Referring to FIG. 1C, a copper seed layer 42 is formed on the conductive barrier layer 30.
Referring to FIG. 1D, a copper layer 44 is formed by an electroplating process using the copper seed layer 42 to fill the opening 26.
Referring to FIG. 1E, the unnecessary portion of the copper layer 44, i.e. the portion above the interlayer dielectric layer 24 around the opening 26, is removed by CMP so that the copper remains only within the opening 26, to form a copper interconnection 44a. 
Referring to FIG. 1F, the conductive barrier layer 30 on the upper surface of the interlayer dielectric layer 24 is removed by CMP to expose the upper surface of the interlayer dielectric layer 24.
Referring to FIG. 1G, a capping insulating layer 50 is formed on the copper interconnection 44a and the interlayer dielectric layer 24.
In the conventional method of forming a metal interconnection as described above, the process of forming the capping insulating layer 50 (FIG. 1G) is typically carried out at a temperature in the range of 350° C. to 400° C. Furthermore, a plasma treatment process is performed to remove a copper oxide layer from the surface of the copper interconnection after the CMP process and before the capping insulating layer 50 is formed. The high process temperature of the plasma treatment and the actions of radicals formed during the plasma treatment process raise the temperature of the wafer, which induces compressive stress in the copper interconnection 44a due to the difference in the coefficients of thermal expansion (CTE) between the copper interconnection 44a and the semiconductor substrate 10. As a result, portions of the copper interconnection 44a rise up at some grain boundary areas, thereby forming features referred to as hillocks.
FIG. 2A is a photograph of the surface of the capping insulating layer showing surface defects caused by the copper hillocks.
FIG. 2B is a photograph of the copper hillocks when the capping insulating layer is removed.
As is clear from these photographs, the capping insulating layer is formed unevenly when the material constituting the capping insulating layer is deposited on a copper interconnection having hillocks. The uneven capping insulating layer may be vulnerable to dry etching. For example, when the etch process is carried out to form a via over the copper interconnection, a weak portion of the capping insulating layer is etched, which may allow the rinse solution or etch solution to penetrate the capping layer and oxidize the copper interconnection. In addition, the oxidized copper interconnection is dissolved and removed during a post rinsing process, which causes a black via phenomenon illustrated in FIG. 3A. Moreover, the hillocks are usually detected as defects only during an inspection that is carried out after the capping insulating layer is formed on the copper interconnection, and mask actual fatal defects. That is, the hillocks impede the ability of inspections associated with each subsequent fabrication process to accurately detect defects.
Also, hillocks are more likely to be formed when the volume of the copper interconnection is large. In other words, hillocks occur more frequently the thicker the copper interconnection and the greater its surface area are. For instance, a dielectric layer of a metal-insulator-metal (MIM) capacitor formed over a copper interconnection may be broken by the hillocks because the MIM capacitor has a large surface area and hence, the copper interconnection must have a correspondingly large surface area and is thus likely to exhibit a great number of the hillocks. In this case, a large amount of leakage current occurs and the capacitor exhibits poor electrical properties. In the case of an inductor where the copper interconnection is 3 to 5 μm thick, the volume of the copper interconnection is thus relatively large. Accordingly, compressive stress is concentrated in the copper interconnection and the hillock problem is exacerbated, as illustrated in FIG. 3B.
Furthermore, in the conventional method, the grain size of the copper layer is very small, e.g. tens of nanometers, due to the characteristics of the electroplating process. Preferably the grain size of the copper layer is enlarged to reduce the resistivity of the copper interconnection. In particular, the copper layer 44 is annealed to enlarge the grain size. The annealing process is carried out at a temperature ranging from about 100° C. to 400° C. However, the large portion of the copper layer 44 disposed outside the opening 26 is over-stressed by the annealing process, causing the portion of the copper layer 44 located in the opening 26 to separate from the interlayer insulating layer 24. This occurs frequently when a fine damascene pattern is formed and the annealing process is carried out at the high end of the temperature range.
In view of this potential problem, the annealing of the copper is generally carried out at the low end of the temperature range, e.g. below 200° C. However, this limits the degree to which the copper grains can be grown. In particular, the grain growth cannot lower the resistivity enough especially in fine patterns, i.e., the conventional method can not realize devices based on small design rules.